Quadruple data rate: Difference between revisions
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'''Quadruple data rate''' (or '''quad pumping''') is a [[microprocessor]] | {{subpages}} | ||
'''Quadruple data rate''' (or '''quad pumping''') is a [[microprocessor]] clocking technique wherein data is transmitted four times for each clock cycle. The [[Front Side Bus]] for [[Intel]]'s [[Pentium 4]] and [[Core 2 Duo]] processors utilizes this technique to achieve an effective 800 MHz (200 MHz × 4),or 1066 MHz (266 MHz × 4). [[Xeon]] processors and future Core 2 Duo processors can reaching an effective 1333 MHz bus (333 MHz x4) with this technique. Quadruple data rate is also used in the [[Accelerated Graphics Port]] (AGP) 4x bus. | |||
Quadruple data rate is not four times as effective as actually increasing the data rate. This is because while the peak bandwidth is quadrupled, the [[Latency (engineering)|read latency]] of the first word is unchanged. This means that although more information is moved, the time between the processor's request and the arrival of the first piece of information is unchanged. However, implementing a quadruple data rate bus is much easier and less expensive than quadrupling the speed of a bus (or doubling the speed of a [[double data rate]] bus). | Quadruple data rate is not four times as effective as actually increasing the data rate. This is because while the peak bandwidth is quadrupled, the [[Latency (engineering)|read latency]] of the first word is unchanged. This means that although more information is moved, the time between the processor's request and the arrival of the first piece of information is unchanged. However, implementing a quadruple data rate bus is much easier and less expensive than quadrupling the speed of a bus (or doubling the speed of a [[double data rate]] bus). | ||
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*[http://safari.oreilly.com/0596003536/pchardnut2-CHP-5-SECT-2 PC Hardware in a Nutshell] | *[http://safari.oreilly.com/0596003536/pchardnut2-CHP-5-SECT-2 PC Hardware in a Nutshell] | ||
* [http://arstechnica.com/articles/paedia/cpu/bandwidth-latency.ars This article] from [[Ars Technica]] provides some grounding in the basics of bandwidth and latency. | * [http://arstechnica.com/articles/paedia/cpu/bandwidth-latency.ars This article] from [[Ars Technica]] provides some grounding in the basics of bandwidth and latency. | ||
Latest revision as of 15:24, 13 November 2007
Quadruple data rate (or quad pumping) is a microprocessor clocking technique wherein data is transmitted four times for each clock cycle. The Front Side Bus for Intel's Pentium 4 and Core 2 Duo processors utilizes this technique to achieve an effective 800 MHz (200 MHz × 4),or 1066 MHz (266 MHz × 4). Xeon processors and future Core 2 Duo processors can reaching an effective 1333 MHz bus (333 MHz x4) with this technique. Quadruple data rate is also used in the Accelerated Graphics Port (AGP) 4x bus.
Quadruple data rate is not four times as effective as actually increasing the data rate. This is because while the peak bandwidth is quadrupled, the read latency of the first word is unchanged. This means that although more information is moved, the time between the processor's request and the arrival of the first piece of information is unchanged. However, implementing a quadruple data rate bus is much easier and less expensive than quadrupling the speed of a bus (or doubling the speed of a double data rate bus).
See also
- Double data rate
- PC Hardware in a Nutshell
- This article from Ars Technica provides some grounding in the basics of bandwidth and latency.