Program counter: Difference between revisions
imported>Howard Arvi Hughes m (fixed cat) |
imported>Ro Thorpe No edit summary |
||
| (4 intermediate revisions by 3 users not shown) | |||
| Line 1: | Line 1: | ||
{{subpages}} | |||
In [[computer science]], the '''program counter''' (PC) is the [[register]] that contains the [[memory]] address of the next instruction to be executed by the [[microprocessor]]. After the typical instruction is executed, the PC is incremented to point to the next instruction. All existing [[instruction set architectures|architectures]] include a method to modify the PC either directly or indirectly---such modifications are referred to as branches or jumps in execution. On some architectures (most notably x86), the PC is referred to as the instruction pointer (IP). | |||
==How it works== | |||
After an instruction is fetched from computer memory by the [[Central processing unit|CPU]] (central processing unit), the program counter is incremented by the length of the instruction word in terms of memory units. Since the program counter counts ''memory addresses'' and not ''instructions,'' it is incremented by the number of memory units that the instruction word contains. In the case of simple fixed-length instruction word [[Instruction set architecture|ISA]]s (instruction set architectures), this is always the same number. For example, a fixed-length 32-bit instruction word ISA that uses 8-bit memory words would always increment the program counter by 4 (except in the case of jumps). | |||
[[ | ISAs that use variable length instruction words, such as [[x86]], increment the program counter by the number of memory words corresponding to the last instruction's length. Also, note that in more complex CPUs, incrementing the program counter does not necessarily occur at the end of instruction execution. This is especially the case in heavily pipelined and superscalar architectures. | ||
Latest revision as of 13:22, 27 July 2008
In computer science, the program counter (PC) is the register that contains the memory address of the next instruction to be executed by the microprocessor. After the typical instruction is executed, the PC is incremented to point to the next instruction. All existing architectures include a method to modify the PC either directly or indirectly---such modifications are referred to as branches or jumps in execution. On some architectures (most notably x86), the PC is referred to as the instruction pointer (IP).
How it works
After an instruction is fetched from computer memory by the CPU (central processing unit), the program counter is incremented by the length of the instruction word in terms of memory units. Since the program counter counts memory addresses and not instructions, it is incremented by the number of memory units that the instruction word contains. In the case of simple fixed-length instruction word ISAs (instruction set architectures), this is always the same number. For example, a fixed-length 32-bit instruction word ISA that uses 8-bit memory words would always increment the program counter by 4 (except in the case of jumps).
ISAs that use variable length instruction words, such as x86, increment the program counter by the number of memory words corresponding to the last instruction's length. Also, note that in more complex CPUs, incrementing the program counter does not necessarily occur at the end of instruction execution. This is especially the case in heavily pipelined and superscalar architectures.